Transaction checking for system architecture validation
US6496792B1 · kind B1 · utility
7Cited by
5References
59Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 1998 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Jul 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a transaction checking for system architecture validation are provided. Tracking data is received from trackers in the system. The tracking data is parsed to construct queues. These queues are compared with each other. For one embodiment, the queues are further compared with predicted behavior of the element that was tested. Discrepancies between the queues and the queue and predicted behavior are flagged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.