Method and apparatus for disabling a processor in a multiprocessor computer
US6496881B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1999 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Mar 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer includes a processor disabling scheme which disables a processor that has been designated to boot the computer but fails to boot the computer. For computers having voltage regulator modules (VRMs) to power each processor, a control device directs a VRM associated with the failed boot processor to cease supplying power in response to the processor's failure. For computers without VRMs, a transistor controls the delivery of power from the power supply to each respective processor. If a designated boot processor fails to boot the system, the control device turns off the appropriate transistor to disable the failed processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.