Patent · US Expired

SRAM bus architecture and interconnect to an FPGA

US6496887B1 · kind B1 · utility

83Cited by
2References
5Claims
0Family size

Assignee

Inventor

Key dates

Filing dateFeb 23, 2000
Grant dateDec 17, 2002
Priority date—
Expiry dateFeb 23, 2020

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K19/1776
  • WIPO fieldBiotechnology
  • WIPO sectorChemistry

Abstract

An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.