Cache memory device
US6496903B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Nov 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory device by which a processing speed can be elevated and which comprises a primary cache memory containing two primary ways of WAY0 and WAY1 each retaining a bit LRU0 and a bit LRU1 taking either a value 0 or 1 together with data and an address, a primary old way determining circuit for determining, on the basis of patterns of the bit LRU0 and the bit LRU1, which is an old way retaining data which has not been accessed for the longest period of time in the primary ways WAY0 and WAY1, and a primary cache control circuit inverting only the bits (the bit LRU0 or the bit LRU1) retained in the old way which has been accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.