Electronic control apparatus with memory validation and method
US6496946B2 · kind B2 · utility
12Cited by
8References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 1999 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | May 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for confirming the operation of memory (212) operates during periods when the memory is not operating in a standard execution mode. This strategy allows the memory to be checked real-time without impacting normal bandwidth of an associated CPU (200). The method and apparatus guarantees deterministic testing by including circuitry and steps which force bus mastership and, therefore, memory access if the memory is busy for too long a period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.