Latch mapper
US6496955B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Oct 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for constructing a latch mapping between a first level description and a second level description of a digital system, wherein the first level description and the second level descriptions identify components in the digital system using a predefined naming convention, is provided. The method includes identifying first latch components in the first level description and, for each identified first latch component, storing a first string comprising a selected property of the first latch component in a first storage. The method further includes identifying second latch components in the second level description and, for each second latch component, storing a second string comprising a selected property of the second latch component in a second storage. The method further includes generating a latch mapping by matching the first strings in the first storage with the second strings in the second storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.