Successive-approximation analog-digital converter and related operating method
US6498579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2001 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Apr 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter. The converter includes a device which enables the increase of the first analog signal in output from the digital-analog converter and in input to the comparator by a preset value (Voffs) when the bit of the first digital signal which corresponds in position to the bit of the second digital signal which must be decided in a clock cycle is zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.