Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same
US6498766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2001 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Jun 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit memory devices include a data latch circuit having a data input, a control input and a clock input, and a strobe signal input buffer. The strobe signal input buffer is preferably responsive to a data strobe signal and an indication signal. The strobe signal input buffer operates as a filter by selectively passing an inactive-to-active transition of the data strobe signal to the control input of the data latch when the indication signal is active, while blocking passage of the inactive-to-active transition of the data strobe signal to the control input when the indication signal is inactive. These filtering operations are preferably performed to inhibit the occurrence of data errors when excessive timing skew is present between a system clock and a data strobe signal at a given rate of speed. Accordingly, the operating speeds of memory devices according to embodiments of the present invention may be reliably increased. The data strobe signal and an unbuffered version of the indication signal are preferably generated by a memory controller, which may be operatively coupled to many memory banks within an integrated multi-bank memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.