Interrupt handler with prioritized interrupt vector generator
US6499078B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1999 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware-implemented interrupt handler external to a processor handles interrupts destined for the processor. The interrupt handler has a programmable prioritized interrupt array with programmable registers that identify priority levels and handling processes for handling one or more interrupts. The interrupt handler also has an interrupt scanning state machine that scans the prioritized interrupt following receipt of an interrupt to extract the priority level and handling process associated with the interrupt. The interrupt handler is designed to handle interrupts in significantly less time than software implementations, thereby making the handler favorable for real time systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.