Post write buffer for a dual clock system
US6499080B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2000 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Jan 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A post write buffer for a dual clock system which improves the utilization of host data bus (10) bandwidth is provided which consists of an address buffer (60), a data buffer (62), a first clock timing signal (22), a second clock timing signal (48), an address decoder (24), a first write enable circuit (72), and a second write enable circuit (74). The address-buffer (60) and data buffer (62). hold the data and the destination address for that data until the clock signals are synchronized and the data is ready for transfer. The address decoder (24) determines which destination register byte will receive the data in the host data bus (10). The write enable circuits (72, 74) synchronize the clock signals (22, 48) and determine when the destination register is ready to receive the data from the data buffer (62).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.