Computer aided design flow to locate grounded fill in a large scale integrated circuit
US6499135B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2000 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | May 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For an integrated circuit having multiple metal layers, a computer-aided design (CAD) method for designing grounded fill in the integrated circuit includes: (a) finding the eligible fill areas for each metal layer; (b) storing the eligible fill area data for each metal layer in an overflow memory; (c) finding ground contact areas for each metal layer; (d) storing the ground contact area data for each metal layer in an overflow memory; (e) temporarily storing the eligible fill area data for a selected metal layer and the ground contact area data for the metal layers adjacent to the selected metal layer in active memory; (f) fitting a fill pattern to an eligible fill area in the selected metal layer, where the fill pattern is composed of at least one element; (g) checking the adjacent metal layers for a ground contact where the element of the fill pattern may be grounded; (h) locating a conductive via between the element of the fill pattern and a ground contact in an adjacent layer; and (i) repeating steps (e) through (h) for each metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.