Face to face chip
US6500696B2 · kind B2 · utility
41Cited by
16References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Oct 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.