Method for fabricating high voltage transistor
US6500716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Mar 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a high voltage transistor includes the steps of: forming a plurality of drift regions on a semiconductor substrate of a first conductive type; implanting drift ions of a second conductive type into surfaces of the drift regions of the semiconductor substrate at a first depth; implanting drift ions of the second conductive type into the surfaces of the drift regions of the semiconductor substrate at a second depth deeper than the first depth; implanting first conductive channel stop ions into the semiconductor substrate thereby forming a space between the semiconductor substrate and the drift regions; forming a device isolation film on a surface of the semiconductor substrate into which the channel stop ions are implanted; forming a gate electrode by inserting a gate insulating film on the semiconductor substrate between the drift regions; and forming a source/drain impurity diffusion region of a second conductive type in the surface of the semiconductor substrate at both sides of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.