Microelectronic fabrication method providing alignment mark and isolation trench of identical depth
US6500725B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Sep 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed simultaneously within the substrate an alignment mark and an isolation trench formed employing a single etch method and to an identical depth within the substrate. There is then formed within the isolation trench an isolation region. Finally, there is then further processed the substrate while aligning the substrate while using the alignment mark in conjunction with a minimum of two alignment wavelengths. The method provides for enhanced efficiency when fabricating the microelectronic fabrication. The method contemplates a microelectronic fabrication fabricated employing the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.