Shallow trench isolation type semiconductor device and method of forming the same
US6500726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 å, preferably 200 å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.