Method for making high voltage device
US6500741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2002 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Mar 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/045
Abstract
An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process. Once the predetermined pattern of dopant material is formed or otherwise deposited upon the upper surface of the epitaxial layer, the substrate, epitaxial and top layers are heated to form a diffusion region in the epitaxial layer, this diffusion region having a specific correlation to the predetermined patter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.