Semiconductor device
US6501098B2 · kind B2 · utility
397Cited by
25References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The gate electrode of a crystalline TFT is constructed as a clad structure which consists of a first gate electrode, a second gate electrode and a third gate electrode, thereby to enhance the thermal resistance of the gate electrode. Besides, an n-channel TFT is provided with a low-concentration impurity region which adjoins a channel forming region, and which includes a subregion overlapped by the gate electrode and a subregion not overlapped by the gate electrode, thereby to mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.