Generation of clock signals for a semiconductor memory that are edge-synchronous with the output signals of a clock generator

US6501308B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS DEUTSCHLAND GMBH · DE

Inventors

• Peter Bakker · Munich, DE
• Fred Rennig · Freising, DE

Key dates

• Filing date: Oct 5, 2001
• Grant date: Dec 31, 2002
• Expiry date: Oct 5, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time. This circuit component (62) is controlled in such a way as to change the signal transit time in inverse proportion to the changes of the output signals of the clock generator (16).