Dynamic duty cycle adjuster
US6501313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Dec 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer. Alternatively, the invention may be implemented in an analog fashion, such as by applying an analog signal to the body contact, wherein the analog signal is generated using an asymmetric charge-pump and filter connected to the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.