High speed input buffer circuit
US6501318B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | May 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09432
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.