Input bias current reduction circuit for multiple input stages having a common input
US6501327B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 10, 2000 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Nov 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/265
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An input bias current reduction circuit for multiple input stages having a common input includes a plurality of input stages each including a first input transistor with its base connected to the common input and the first current sensing transistor with its collector-emitter in series with the collector-emitter of the first input transistor and its base current replicating that of the first transistor; and a current compensation circuit for sensing the base current of the first current sensing transistor in each input stage and subtracting that from the base current of the first input transistor in each input stage for maintaining constant reduced current loading of the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.