Correction of operational amplifier gain error in pipelined analog to digital converters
US6501400B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | May 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/442
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipeline analog to digital converter that includes a main pipeline including a plurality of analog to digital converter stages and a shadow pipeline for compensating the output of the main pipeline. Each of the analog to digital converter stages in the main pipeline provides a digital output and an analog residue signal. The shadow pipeline includes one or more stages that receive at least one gain error signal from one of the analog to digital converter stages in the main pipeline. The shadow pipeline is configured and arranged to processes the gain error signal to form a compensation signal. The compensation signal is combined with the analog residue signal to provide a compensated residue signal in which the finite error gain has been substantially removed. Alternatively, the compensation signal may be converted into a digital format and combined with the digital output bits of one or more of the analog to digital converter stages in the main pipeline to provide a compensated digital output that has had substantially all of the gain error removed therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.