Circuit arrangement for the lowering of the threshold voltage of a diode configured transistor
US6501673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.