Loadable divide-by-N with fixed duty cycle
US6501815B1 · kind B1 · utility
8Cited by
8References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit configured to generate an output signal having a first frequency in response to a clock signal having a second frequency. The output signal may be in a first state and a second state for an equal number of half-cycles of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.