Memory system including a point-to-point linked memory subsystem
US6502161B1 · kind B1 · utility
430Cited by
5References
49Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2000 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Jan 5, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.