Method and system for check stop error handling
US6502208B1 · kind B1 · utility
27Cited by
49References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system aspects for check stop error handling are provided. A method aspect for check stop error handling in a computer system, the computer system comprising a plurality of components including a processor that supports an operating system and firmware, includes utilizing a service processor following a check stop error for error data retrieval and attempting a reboot of the computer system. The method further includes initiating firmware for failure reporting based on the error data retrieval when the reboot is successful.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.