Embedding parasitic model for pi-fet layouts
US6503774B2 · kind B2 · utility
4Cited by
1References
7Claims
0Family size
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Key dates
| Filing date | Apr 23, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Apr 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/316
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A model for a semiconductor device and more particularly to a Pi-FET with multiple gate fingers. The model takes into account various parasitics and the inter-relationship therebetween. In particular, multi-finger Pi-FETs are modeled as multiple single finger unit cells. Each single unit cell takes into account off-mesa parasitics, inter-electrode parasitics, on-mesa parasitics and includes an intrinsic model which represents the physics that predominantly determine FET performance. As such, the model can be used for relativity accurate device technology modeling, optimization of device performance and device design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.