Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning

US6503840B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Wilbur G. Catabay · Saratoga, US
• Wei-Jen Hsia · Sunnyvale, US
• Hong-Qiang Lu · Fremont, US
• Yong-Bae Kim · Cupertino, US
• Kiran Kumar · Kanchinakote, IN
• Kai Zhang · Shanghai, CN
• Richard Schinella · Saratoga, US
• Philippe Schoenborn · San Jose, US

Key dates

• Filing date: May 2, 2001
• Grant date: Jan 7, 2003
• Expiry date: Jul 10, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31138
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nit…