Integrated circuit having a balanced twist for differential signal lines
US6504246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1999 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A balanced twist design for differential small signal pairs which is balanced in terms of resistance, capacitance and process variance. In the twist design of the present invention, each routing (6, 10) passes through two layers of metal. In addition, each routing (6, 10) passes through the same number of vias (9, 13, 14, 15), and experiences the same number of bends. Each routing (6, 10) is also exposed to the same sidewall crosstalk since the length and width of each routing (6, 10) in both metal layers is approximately the same. As a result, the new twist design reduces signal degradation, enhances signal separation, and allows increased clock speed of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.