Buffer improvement
US6504413B1 · kind B1 · utility
0Cited by
6References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Mar 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a buffer improvement for higher speed operation. A buffer may include at least two buffer stages, which may include a first buffer stage and a second buffer stage. A voltage conversion circuit is disposed between the first buffer stage and the second buffer stage. The voltage conversion circuit is suitable for acting as a delay between the first buffer stage and the second buffer stage. Additionally, the first buffer stage may be driven directly, thereby increasing buffer speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.