Low-noise, fast-lock phase-lock loop with “gearshifting” control
US6504437B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0898
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-lock loop (PLL) circuit provides fast locking and low spurious modulation jitter through “gearshifting” control. The gearshifting PLL combines the advantages of low jitter from integer-N PLL and fast locking from fractional-N PLL. The PLL circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). Control of the PLL circuit includes configuring the PLL circuit in two configurations, one for each phase of operation. The bandwidth of the loop filter is increased during the first phase of operation and the circuit is locked to a frequency that is close to the desired output frequency. During the second phase, the bandwidth of the loop filter is decreased and the circuit is locked to the desired frequency. The first configuration provides a relatively fast lock time compared to the lock time provided by the second configuration. The second configuration provides more stability than the first configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.