Addressing methods for displays having zero time-average field
US6504524B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Mar 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0204
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Novel addressing schemes for controlling electronically addressable displays include the use of addressing signals with additional signals having opposite polarity and equal integrated signal strength and addressing schemes that minimize the number of state changes that a display element undergoes. In one embodiment, pre-pulses are employed to apply a pre-stress to an display element that is equal and opposite to the electrical stress applied in addressing the element. In another embodiment, the addressing signal is followed by a post-stressing pulse. Methods for minimizing the number of display elements that must change state to change the image displayed include the determination of a set of elements that must be deactivated and a set of elements that must be activated to change the image depicted by a display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.