Bitline precharge
US6504775B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Sep 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitlines architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other. To ensure that all four bitlines equalize to the midpoint voltage level, complementary logic levels are written to the bitlines prior to equalization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.