Three-dimensional interconnection geometries for multi-stage switching networks using flexible ribbon cable connection between multiple planes
US6504841B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1999 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Oct 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5627
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred “layered network” of U.S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U.S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.