Method of testing an evaluation circuit
US6505136B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | May 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3277
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention concerns a method of testing an evaluation circuit (10 11), which checks the correct contact of a switch (13) with a testing means (14) in a d.c.-supplied circuit. The testing means (14) includes for example a capacitor (15) in parallel with the switch (13). The evaluation circuit (10) itself is made up of a controller (11), an input and an output buffer (17 18). To determine faulty conditions in the output buffer (17), the invention arranges that when testing for faults both the input and the output buffer (17 18) be actively connected by connecting them connected to the controller (11) via a respective data line (21 21a) for exchanging data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.