Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
US6505269B1 · kind B1 · utility
43Cited by
155References
20Claims
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Key dates
| Filing date | May 16, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic address mapping technique eliminates contention to memory resources of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The technique defines two logical-to-physical address mapping modes that may be simultaneously provided to the processors of the arrayed processing engine to thereby present a single contiguous address space for accessing individual memory locations, as well as memory strings, within the memory resources. These addressing modes include a bank select mode and a stream mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.