Register renaming to optimize identical register values
US6505293B1 · kind B1 · utility
44Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor architecture for providing many-to-one mappings between logical registers and physical registers, so that more than one logical register may map to the same physical register. Each physical register has an associated counter to indicate whether the physical register is free. A counter is incremented each time a mapping is made to its associated physical register, and is decremented when that mapping is no longer needed. If a logical register named in a decoded instruction is predicted to have the same value as a value stored in a physical register, then the logical register is mapped to the physical register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.