System and method for testing signal interconnections using built-in self test
US6505317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Mar 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system. A master and a slave chip need not be mounted upon the same circuit board, allowing for tests through connectors within a computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.