Logic circuit design method and cell library for use therewith
US6505322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jul 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.