Semiconductor with nanoscale features

US6506660B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Steven J. Holmes · Colchester, US
• Charles T. Black · White Plains, US
• David J. Frank · Yorktown Heights, US
• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• David V. Horak · South Burlington, US
• William H. Ma · Wappingers Falls, US
• Keith Milkove · Beacon, US
• Kathryn Guarini · Yorktown Heights, US

Key dates

• Filing date: Nov 13, 2001
• Grant date: Jan 14, 2003
• Expiry date: Nov 13, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.