Multi-layer wiring substrate and manufacturing method thereof
US6506982B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Feb 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09854
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows. Subsequently, second windows of a particular shape are provided in regions of layers of the insulating resin filled in the windows, and independent conducting paths are formed through the second windows to extend from front sides of the second windows to back sides thereof. The conducting paths are formed radially to be spaced a substantially equal distance from centers of the res…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.