Semiconductor memory device
US6507124B2 · kind B2 · utility
5Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Jun 8, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p+ type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.