Buffer circuit
US6507519B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Sep 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/771
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A buffer circuit includes a MOSFET source follower (M54) and a floating gate MOSFET (MFG53) connected in series with the phototransistor (PT51) to control current through it at an input circuit node (D53). The source follower (M54) buffers the phototransistor (PT51), having a gate (G54) connected to its emitter (PC51). The floating gate (F53) is programmable with charge to preset the phototransistor current under prearranged illumination conditions to counteract unwanted signal contributions (e.g. fixed pattern noise) or non-optimum circuit characteristics. The floating gate MOSFET (MFG67) may alternatively be connected in series with the source follower output (D65) to control current at an output circuit node. The circuit may be a member of a pixel circuit array and may include programming circuitry (M84, M85) to select it for programming and to isolate it to enable other array members to be programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.