Nonvolatile memory system
US6507520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Dec 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.