Switching method in a multi-threaded processor
US6507862B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1999 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | May 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.