Method and apparatus for access demarcation
US6507895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.