Reconfigurable data cache controller
US6507898B1 · kind B1 · utility
79Cited by
140References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1998 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/90
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for supplying multiple, separately addressed data items from a data table in external memory.The apparatus comprises a cache memory (230) having n separately addressable memories banks organised as m cache-lines and n programmable address generators (1881) each coupled to a corresponding one of said n memory banks. The generators (1881) using an index to generate multiple addresses to simultaneously retrieve multiple data items from the memory banks. A data organizer (1892) positions the retrieved data in an output packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.