Trace fifo management
US6507921B1 · kind B1 · utility
58Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO (800) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M+K, P+Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC13LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P+Q).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.