System and method for diagnosing and repairing errors in complementary logic
US6507929B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1999 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Mar 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition at the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a defect during normal runtime operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.