Timing verifying method
US6507936B2 · kind B2 · utility
15Cited by
2References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Aug 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with a timing verifying method of the present invention, the step of calculating a variation delay time composed of a wire delay time and a cell delay time in consideration of a process varying condition is performed independently of the step of performing logic simulation of a semiconductor integrated circuit based on the calculated variation delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.